Module 1Apple Board-Level Repair/
DAY 02 / 08BLOOM · APPLY~9 MIN READ
Phase 1 — Reading the Mainboard Schematic & Card

Decode the structure and language of the Apple logic board schematic

◇ OPENING ◇
HOOK · GAP

You know electronics: you can explain what voltage, current, and resistance are, and what a capacitor does. But the first time you open a real Apple logic board schematic — say the 85-page schematic of the iPhone X — you freeze for a moment. Dozens of pages, hundreds of abbreviations, a wire starts somewhere and vanishes before it ends. 'How am I going to read this?' Here is the gap: knowing electronics does not mean knowing how to read this DOCUMENT. A schematic is a document with its own language — it has its own map (page layout), its own alphabet (symbols, designators), and its own grammar (net names, 'invisible' connections). Today we descend to the first step of yesterday's flow, READ, and decode this language: how an Apple schematic is organized, and what the letters/names/lines on the page tell. Once you crack this language, tomorrow you'll be able to follow a trace across pages — and the schematic stops being a maze and turns into a roadmap.

01 · QUESTION
CONCEPT

Why is an Apple logic board schematic not a single page, and how is it organized?

A simple circuit fits on one page. But an Apple logic board carries hundreds of chips and thousands of connections — so the schematic is multi-page (iPhone X = 85 sheets). What doesn't fit in a single picture is split into an organized document:

  • Table of contents (ToC): Which block is on which page? Like 'charging sheet 23, NAND sheet 16'. You go to the block you're looking for from here — the first stop before diving into the circuit.
  • Sheets: Each page is a block/function (power, SOC, camera...). In its corner there is a title block (page name + number).
  • Testpoint / probe pages: A map of the points to be measured — useful in the MEASURE step.
  • Bootstrapping / config page: BOM options, fuse/variant settings — the board's 'personalization' notes.

The most critical point — how pages connect: A net (signal/rail) can start on one page and continue on another. This is managed by the off-page connector (off-page connection arrow) and the cross-reference page number beside it: 'this trace comes from sheet 17 / goes to sheet 40.'

Today's question: If we decode the structure (map) and the language (alphabet + grammar) of this document, can we find our way even on a page we don't know?

Multi-page + cross-reference is the foundation of tomorrow's trace following: following a trace from both ends becomes possible across pages through these arrows.

02 · QUESTION
REFERENCE

The alphabet of the schematic: what do designator letters tell?

Each part has two labels: a name (designator) and a value. The first letter of the designator tells the type of the part — this is universal and standard:

Letter Part type
R Resistor
C Capacitor
L Coil/inductor
D Diode
Q Transistor
U Integrated circuit (IC)
Y Crystal/oscillator
J Connector (jack/socket)
S Switch

Each name is unique (R1, R2, R3...) and is the address for finding that part on the board. The value is the part's most important property: ohms for a resistor, farads for a capacitor, the chip name for an IC, frequency for a crystal.

How you see this on an Apple board (real iPhone X examples):

  • U1000 = an IC (the A11 processor). U2700 = an IC (PMU).
  • J3200 = a connector (battery). J5700 = connector (display).
  • Y1000 = a crystal (24 MHz). L6110 = a coil (0.47 µH). Q3350 = a transistor (BATFET).
  • R5901 = a resistor. C... = capacitor.

Reading tip: When you see a designator, first read the letter — you instantly know the part type (U=chip, J=connector, L=coil). Since the IC symbol is always the same (a pinned rectangle), what identifies an IC is the designator + value (chip name). The designator points to the same part in the schematic, in the boardview, and on the physical board — the address that links the three worlds.

03 · QUESTION
REFERENCE

How do net names and the 'invisible connection' work?

Net = an electrical node connecting two (or more) terminals to each other; shown with a line in the schematic. Two rules:

  • Node/dot: At a crossing of two lines, if there is a dot they are connected; if there is no dot the wires just pass over each other and are not connected. This distinction is critical.
  • Net name/label — the most important rule: Nets with the same name are connected to each other even if there is no visible wire between them. Instead of drawing everything with wires in a complex schematic, a net is given a name; every place carrying the same name is the same net.

Nets are named by their function (SparkFun example: VCC, 5V, RX, TX). On an Apple board this language is richer:

  • Power rails start with PP_: PP_VDD_MAIN (the main backbone), PP3V0_NAND, PP_BATT_VCC. Voltage/function is read from the name.
  • Signals by function: SPMI... (PMU communication), PCIE_AP_TO_BB (A11→baseband data).
  • _L suffix = active-low: the signal is active when it is low (0) (e.g. ..._RESET_L resets when low). This suffix is very common at the board level.
  • Ground (voltage node): GND/IOG — single-terminal symbol; every same-named ground is connected.

Reading tip — tomorrow's key: The 'same name = connected' rule means that a net appearing with the same name on sheet 5 and on sheet 40 is the same net. The off-page connector + cross-reference page number manages exactly this. That's why you can follow a trace across pages (tomorrow): you follow the net name, not the wire.

INTERACTIVE
Pick the net on the left, connect its same-named twin on the right page. Same name = same net (even without a wire); if the name doesn't match exactly, it's a different net. You follow a trace across pages by its name.
04 · QUESTION
PROCEDURE

How do you find your way on an Apple schematic page you don't know?

You've opened a schematic page you've never seen before. No panic; use the document and the language.

Step 1 — Locate yourself: Look at the page's title block (which block, which sheet number). If needed, go back to the ToC and see where this block fits.

Step 2 — Recognize the parts: Scan the designator letters — the U's (chips) are the page's 'players', the J's (connectors) are input/output, L/R/C are peripheral components. A large U is usually the page's main chip.

Step 3 — Read the nets: Look at the net names. Those starting with PP_ are power; those ending with _L are active-low; function names (RESET/CLK/DATA) tell the signal's job. Check whether there's a dot (connected) / no dot (not connected).

Step 4 — See the off-page: If a net goes toward the edge and ends with an off-page connector + cross-reference page number, that net continues on another page. Note its name — tomorrow you'll follow that name.

Step 5 — Summarize: 'This page describes this block; the main chip(s) are these; this net comes in here, that net goes to that page.' If you can describe the page in one sentence, you've found your way.

DO IT NOW · THOUGHT EXPERIMENT
10 MIN

Decode schematic elements by their language

On a schematic page you see the following. Write briefly what each one tells: (a) a pinned rectangle labeled `U2700`. (b) The text `PP_VDD_MAIN` on a line, the same text also present two pages away. (c) A signal named `AP_TO_BB_RESET_L`. (d) Where two lines cross, there is NO dot.

TOOL LIST
schematic/boardview softwareiPhone X schematic (PDF, example)
EXPECTED OUTPUT

(a) U = integrated circuit (IC); `U2700` is that chip's unique address (the same on the board/in the boardview). Since the symbol is generic, the value/chip-name identifies the chip. (b) `PP_` = power rail (main backbone supply); if the same name appears on two pages, by the 'same name = connected' rule it is the SAME net, even without a wire between them. (c) `_L` suffix = active-low; the signal resets when low (0) (A11→baseband reset). (d) No dot → the two wires are NOT connected, they just pass over each other. The answers should correctly apply the designator/net-name/node rules.

VERIFICATION

Compare each of your answers against Sections 2-3: check that you correctly decoded the designator letter (U=IC), the `PP_`/`_L` net language, and the dot-present/absent connection rule; especially that in (b) you made the 'same name = connected' and in (d) the 'no dot = not connected' distinction.

COMMON MISTAKE · PROCESS ERROR
FB ARCHIVE

Assuming a net exists only where you see the wire

While following a supply rail, a beginner assumed the trace 'ended' at the edge of the page and stopped the search there. But the trace didn't end: through an off-page connector it continued on another page under the name `PP_VDD_MAIN` — 'same name = connected'. Because they searched for the net only as a line, they never saw the real source (on another page) and blamed the wrong block. Another time, they assumed a dot-less crossing was 'connected' and reasoned over a connection that didn't exist.

WHY IT'S WRONG

An Apple schematic is multi-page and nets are mostly connected by **name**, not by wire. Limiting a net to only the line you see misses the cross-page 'invisible' (same-named) connections — making you look for the source/load in the wrong place. Conversely, assuming a dot-less crossing is connected builds a circuit that doesn't exist. When the two rules (same-name-connected + dot-connected) are skipped, the reading is wrong from the start.

CORRECT REFLEX
  • Follow the net as a NAME, not a line: the same name on different pages = the same net.
  • Always follow the off-page connector + cross-reference page number at the edge.
  • Check whether there's a dot at the crossing: dot=connected, no dot=not connected.
05
REFERENCE

What is today at a glance?

The essence of today — the map + language of the document:

  • Document structure: An Apple schematic is multi-page (iPhone X = 85 sheets); ToC (which block is where) + sheets (each one a block) + testpoint pages + bootstrapping/config. Pages connect via off-page connector + cross-reference page number.
  • Designator language: First letter = part type (R/C/L/D/Q/U/Y/J/S); name unique and the 'address'; value = the most important property (chip name for an IC). Apple: U1000/J3200/Y1000/L6110/Q3350.
  • Net language: Line=net; dot=connected, dot-less crossing=not connected; same name = connected (even without a wire). Apple: PP_ power rails, _L active-low, function-named signals, GND/IOG ground.
  • Finding your way: title block → designators (players) → net names (jobs) → off-page (where it goes).

You got to know the document and learned its language. Tomorrow we put this language into motion: following a net from both ends — from its source to its load — across pages. Today's 'same name = connected' rule is the very engine of that following.

DAY SOURCES
◇ CLOSING ◇
STANDARD CLOSING · K11.A

What did you gain today?

CONCEPT SUMMARY

What you learned today

  • An Apple schematic is multi-page (iPhone X = 85 sheets): ToC (block→page) + sheets + testpoint + bootstrapping/config; pages connect via off-page connector + cross-reference page number.
  • Designator language: first letter = part type (R/C/L/D/Q/U/Y/J/S); name unique and the 'address'; value = the most important property (chip name for an IC). Apple: U1000/J3200/Y1000/L6110/Q3350.
  • Net language: dot = connected, dot-less crossing = not connected; same name = connected (even without a wire). Apple: PP_ power rails, _L active-low, GND/IOG ground.
  • Finding your way: title block → designators (players) → net names (jobs) → off-page (where it goes).
CASE

A moment from the field

An apprentice following a supply rail assumed the trace 'ended' at the edge of the page and stopped searching. But the trace continued on another page under the name `PP_VDD_MAIN` through an off-page connector — same name, same net. Because they searched for the net only as a line, they never saw the real source and blamed the wrong block. The master followed the net by its name, followed the cross-reference, and found the source two pages away. When the schematic's language (same-name-connected) isn't known, even the simplest follow goes to the wrong place.

TOMORROW

What will you learn tomorrow?

You got to know the document and learned its language. Tomorrow we put this language into motion: **trace following** — following a net from both ends, from its source to its load, across pages. Today's 'same name = connected' + off-page connector rules are the engine of that following; now you'll be able to work out where a trace comes from and where it goes.

MENTAL BRIDGE

Yesterday you mapped out the flow (READ→MEASURE→INSPECT→DECIDE→INTERVENE); today you built the first half of the 'READ' step — the document and its language. Once a designator settles in your mind as an 'address', a net name as a 'job', and an off-page as a 'continuation arrow', the schematic is no longer a maze but a readable map. Tomorrow you'll actually walk on this map (trace following).

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