Two programs, two separate paths

Open any one to see what is inside it.

1. P1Measurement and System Fundamentals14 d▶

   Core starter phase spanning safety to measurement and basic components to system thinking.

   1. 01Define the ESD-safe workshop discipline
   2. 02Explain electricity as charge flow and interpret the complete circuit
   3. 03Explain the LED current-limiting resistor with Ohm's Law
   4. 04Explain the resistor power threshold with P = V × I
   5. 05Choose multimeter modes and apply the Vcc-GND measurement
   6. 06Compute and measure the equivalent resistance in series-parallel circuits
   7. 07Identify the resistor and capacitor from visual codes, and measure with a multimeter
   8. 08Determine diode orientation and test diode health with diode mode
   9. 09Build and test how a BJT and MOSFET work as switches on a breadboard
   10. 10Systematically measure and map Vcc and GND lines on an unknown board
   11. 11Systematically measure and apply the distinction between short, open, and intermittent faults with a multimeter
   12. 12Apply the schematic language and read the ATmega328P minimum circuit
   13. 13Recognize solder quality and apply a safe protocol
   14. 14Test Phase 1's 13-day accumulation on the first real fault case and bridge to Phase 2

1. P2Processor Systems14 d▶

   Teaches the processor as a living system with power, reset, clock, boot and IO prerequisites. Bus logic is introduced as needed; depth follows in Phase 3.

   1. 01Explain the ATmega328P pinout and interpret it through modern processor pin groups
   2. 02Read the VCC, AVCC, GND, and AREF power lines on the ATmega328P and interpret them through modern SoC multi-rail architecture
   3. 03Read the ATmega328P RESET pin, the pull-up resistor, and the RST signal, and interpret them through the reset chain on modern Intel laptop platforms
   4. 04How the ATmega328P produces the clock signal on XTAL1, XTAL2, and the 16 MHz crystal, interpreted through the TCXO + PLL tree of MediaTek Dimensity
   5. 05Read the ATmega328P ROM, fuse, flash, and bootloader chain, and interpret it through the iBoot chain of Apple M-series Macs
   6. 06Tell apart VIL, VIH, HIGH, and LOW levels on the ATmega328P GPIO pin, and interpret them through the modern Apple A-series GPIO block
   7. 07Apply ATmega328P GPIO output in push-pull and open-drain modes to a board with DDRx and PORTx, and compare it with the modern Snapdragon TLMM block
   8. 08Apply ATmega328P UART communication to a board with the USART registers, baud rate, and start/stop framing, and compare it with the legacy Intel COM port
   9. 09Apply ATmega328P multi-device communication on the I²C-bus with the TWI registers, pull-up resistors, and 7-bit addressing to a board, and compare it with the MediaTek mobile SoC I²C topology
   10. 10Apply ATmega328P SPI communication to a board with the SPCR, SPSR, SPDR registers, the CPOL/CPHA modes, and chip select, and compare it with the Apple M-series Mac SPI flash boot architecture
   11. 11Apply ATmega328P GPIO interrupt INT pins, DRDY, and handshake signals on a board, and compare them with the handshake discipline between modules inside a Snapdragon SoC
   12. 12Apply ATmega328P SMCR sleep mode, wake-up sources, and low-power current measurement to a board, and compare it with the Intel C-states and ACPI architecture
   13. 13Apply the VCC RESET CLOCK BOOT DATA 5-ring diagnostic order on the ATmega328P to a broken board, and compare it with the same 5 rings in the MediaTek Dimensity SoC architecture
   14. 14Phase 2 synthesis: evaluate the ATmega328P 5-ring diagnostic protocol in the same table across the Apple A-series, Apple M-series, Snapdragon, MediaTek, and Intel architectures
2. P3Communication Debug and Signal Analysis14 d▶

   UART/I²C/SPI protocol debug with logic analyzer and oscilloscope, signal/power integrity diagnosis and bus analysis through a repair technician's lens with real fault cases.

   1. 01Explain a logic analyzer capture
   2. 02Explain oscilloscope probe errors
   3. 03Apply UART garbage-character diagnosis
   4. 04Apply ACK and NACK results with the I²C scanner
   5. 05Apply I²C stuck bus recovery
   6. 06Calculate the pull-up value with the datasheet
   7. 07Measure the SPI mode setting with a logic analyzer
   8. 08Separate a wrong SPI flash read
   9. 09Measure a timing violation with trigger and pulse capture
   10. 10Measure trace reflection with probe and impedance mismatch
   11. 11Measure rail stability
   12. 12Measure the crosstalk symptom
   13. 13Apply the bus debug flow
   14. 14Apply the I²C touch debug flow
3. P4Peripheral Diagnosis14 d▶

   From what the user sees to what the subsystem says — 5-step meta-diagnosis and fault-matrix reflex across sensor, touch, display, camera, audio, battery, thermal and port subsystems.

   1. 01Explain a peripheral symptom
   2. 02Explain the sensor chain through transducer, ADC, and the data path
   3. 03Explain the detect chain through proximity, Hall, and lid switch links
   4. 04Explain the touch chain through panel, controller, and reference
   5. 05Separate the black screen into backlight, TCON, and panel supply
   6. 06Separate the camera chain through the module, flex, and MIPI clock lane
   7. 07Separate the audio chain
   8. 08Examine fuel gauge trust
   9. 09Separate thermal shutdown into throttle and protection shutdown
   10. 10Separate accessory recognition into port, detect line, and signature
   11. 11Separate the partial symptom in the power, data, and peripheral layers
   12. 12Set up the measurement order
   13. 13Part installed but not working — apply the 5 rules
   14. 14Measure and compare peripheral diagnosis across 5 brands
4. P5Wireless and Higher Layers14 d▶

   Six-link RF chain, Wi-Fi/BT/NFC/cellular modules, USB-PD negotiation, Type-C CC pin, charging IC, wireless charging, coexistence and a 5-step RF diagnostic flow — parallel learning across 5 brands.

   1. 01What is a wireless signal and through which path does it reach the processor?
   2. 02How does an antenna work, and why is impedance matching important?
   3. 03What roles do the PA, LNA, and switch play in the RF front-end?
   4. 04Through which line does a Wi-Fi module talk to the processor?
   5. 05How are pairing and data flow set up on a Bluetooth module?
   6. 06How do the NFC antenna and controller work in the near field?
   7. 07The logic of baseband: how does the cellular network connect to the processor?
   8. 08Explain the USB-PD negotiation through its four-message flow
   9. 09Explain the USB Type-C CC lines through orientation detection and Rp/Rd logic
   10. 10Explain the charging controller through CC/CV, NTC, and protection layers
   11. 11Explain wireless charging through coupling, Qi, and alignment
   12. 12Coexistence: how do Wi-Fi and Bluetooth live in the same 2.4 GHz band without colliding?
   13. 13Evaluate wireless-module diagnosis through a systematic flow
   14. 14Evaluate the transition from the wireless layer to mainboard literacy
5. P6Logic Board Literacy14 d▶

   Five capabilities: 5 board regions (physical map) + 5 schematic sections (logical map) + IEC 60617 symbol alphabet & net names + boardview/designator/test point/trace following + 5-step measurement plan + BGA triple evidence. Parallel literacy across 5 brands.

   1. 01Motherboard literacy: explain why a board can be read like a map.
   2. 02Interpret the five sections of the STM Nucleo schematic by starting from the right questions.
   3. 03Explain the IEC 60617 symbol language on an Arduino schematic through 12 main symbols.
   4. 04Interpret the net names on the STM Nucleo schematic by their role families.
   5. 05Explain the boardview tool as the mapping layer between the schematic and the physical board.
   6. 06Interpret the reference designator families on the STM Nucleo schematic per the IPC-7351 standard.
   7. 07Apply the measurement-point hierarchy across four boards: Test Point (TP), via, pad, IC pin.
   8. 08Apply following a net as a physical trace from source to load on the STM Nucleo schematic.
   9. 09Examine the measurement differences on the same net of a golden board vs. a faulty board by analyzing them.
   10. 10Apply the five steps of the measurement plan in order against a symptom: hypothesis, schematic section, measurement point, evidence, decision.
   11. 11Apply schematic and boardview together on a single net: fluent transition between the logical map and the physical map.
   12. 12Analyze Phase 6's 5 capabilities by examining them in parallel across 5 different board types.
   13. 13Evaluate the integrity of an invisible trace beneath a BGA package via a triple evidence chain of schematic + boardview + surrounding-TP measurement.
   14. 14Evaluate Phase 6's 5 capabilities by combining them in a single case — build the bridge to Phase 7 reading-before-intervention.
6. P7Controlled Intervention14 d▶

   1. 01How Do You Build the Pre-Intervention Risk Map?
   2. 02How Do You Set the Soldering Station's Temperature and Air Flow?
   3. 03How Do You Build the Discipline of Working Under a Microscope?
   4. 04By Which Techniques Is an SMD Component Removed and Placed?
   5. 05How Do You Compute the Hot Air Profile for BGA Removal?
   6. 06How Are the Stencil and Solder Paste Aligned in BGA Reball?
   7. 07Which Task Does Each Flux Type Take On at Which Temperature?
   8. 08How Do You Evaluate the Method-Risk Matching in Underfill Removal?
   9. 09How Do You Explain Via and Pad Damage Repair Techniques?
   10. 10How Do You Sequence the UV-Cure Solder Mask Damage Repair Steps?
   11. 11How Do You Evaluate the Neighboring IC Thermal Risk During Intervention?
   12. 12How Do You Evaluate the Irreversible Steps in the Intervention Flow?
   13. 13In Which Order Do You Sequence the 4-Layer Post-Intervention Verification Test?
   14. 14F7 Synthesis: How Do You Evaluate the 14 Days in the Three-Surface × Five-Question Matrix?
7. P8Synthesis and Specialization14 d▶

   1. 01What Flow Does the Unified F1-F7 Diagram Describe?
   2. 02How Do the 7 Concepts Learned on the ATmega328P Grow Inside Modern SoCs?
   3. 035 Architectural Approaches Compared — Apple, Samsung, Qualcomm, Intel, MediaTek Side by Side
   4. 04At Which Steps Does the Boot Chain Differ Across the 5 Brand Processors?
   5. 05How Do You Compare PMIC and Power-Tree Topology Across 5 Brands?
   6. 06Which Specs Are Applied in 5-Brand Communication Architectures?
   7. 07Single Case Study — Which Flow Resolved the 302 FB Fault?
   8. 08In the 302 FB Case, Which Phase 1-7 Knowledge Was Used at Which Moment?
   9. 09Bridge to iPhone Curriculum — Which Topics Map Where?
   10. 10Bridge to iPad Curriculum — Which Historical Data Matters?
   11. 11Bridge to MacBook Curriculum — What Architectural Differences Exist?
   12. 12Which Curriculum Topics Require Continuous Updating?
   13. 13Design your professional practice plan: dos and don'ts
   14. 14Phase 8 Synthesis (Capstone): USTA Academy Completion — Which Competency Profile Emerged?

Open any one to see what is inside it.

1. M1Schematics & Card Reading8 d▶

   Reading Apple board schematics and the physical card + rework basics (model-agnostic)

   1. 01Map out the repair workflow and the tool landscape
   2. 02Decode the structure and language of the Apple logic board schematic
   3. 03Trace a rail from its source to its load, from both ends
   4. 04Map the power tree from its source to its loads
   5. 05Locate the measurement point on the schematic, boardview, and board triangle
   6. 06Interpret measurement modes and readings according to the situation
   7. 07Read the visual evidence and make the rework decision
   8. 08Set the rework parameters and heat to match the job

   The OKU→ÖLÇ→İNCELE→KARAR→MÜDAHALE backbone.

   Electronics knowledge is a prerequisite; tools/measurement/rework at parameter+concept level (not a hand-technique tutorial).

1. M2iPhone Mainboard Specialization17 d▶

   17-day iPhone board-level specialization reading a real iPhone logic-board schematic page by page

   1. 01Document structure: orientation, BOM and test points
   2. 02SOC interfaces: PCIe, MIPI/ISP, serial, GPIO
   3. 03SOC power rails (supply families)
   4. 04PMU: buck/LDO power map
   5. 05The main power backbone (battery, Tigris, boost)
   6. 06The wake chain: power button → PMU → AON
   7. 07NAND and the boot loop
   8. 08Display and touch (Hawking)
   9. 09Face ID (Pearl: Rigel, Romeo, Juliet)
   10. 10Camera and flash
   11. 11Sound and vibration (codec + Taptic)
   12. 12Sensors (Graphite and others)
   13. 13Dual logic board and the interposer bridge
   14. 14Baseband modem (BBPMU)
   15. 15RF: transceiver, PA and antenna
   16. 16Wi-Fi / NFC / GPS (Guinness)
   17. 17Full device diagnosis (capstone)

   Core skill: net/rail tracing (source↔load, cross-reference) and the power+data+control three legs per block; pairing/two-board limits.

2. M3iPad Mainboard Specialization15 d▶

   1. 01Document structure and boot/board ID
   2. 02SOC interfaces: PCIe, MIPI/ISP, serial, GPIO
   3. 03SOC core power rails (CPU/GPU/SOC)
   4. 04PMU: buck/LDO power map
   5. 05Main power backbone (PP_VDD_MAIN, battery, boost)
   6. 06Wake chain: power button → PMU → AOP
   7. 07NAND and boot (boot-config)
   8. 08Charging: Lightning, Tristar, and Tigris
   9. 09Display and backlight
   10. 10Touch and Home/Touch ID
   11. 11Camera (MIPI/I2C)
   12. 12Audio: codec and speaker amplifier
   13. 13Sensors (AOP)
   14. 14Wi-Fi / Bluetooth (no baseband)
   15. 15Full iPad 7 diagnosis (capstone)

   iPad (Wi-Fi model) board-level delta: reading a real logic-board schematic that shares the same core generation, page by page, baseband-free.

   Core skill: net/rail tracing (source↔load) and the power+data+control three legs; the Wi-Fi model drops baseband/NFC/cellular blocks.

3. M4MacBook T2 Mainboard18 d▶

   18-day MacBook board-level specialization reading a real MacBook logic-board schematic FOLLOWING THE SCHEMATIC'S OWN TOC ORDER, each section by its own sheet name

   1. 01Document structure: table of contents, BOM and mechanicals
   2. 02The Processor (CPU): graphics, memory and power
   3. 03The chipset (PCH): USB, clocks and power management
   4. 04LPDDR3 memory: channels, VREF and termination
   5. 05USB-C and Thunderbolt
   6. 06Wi-Fi / Bluetooth module
   7. 07T2 logic and communication (GPIO, SMC, I2C/SPI)
   8. 08T2 power and support (boot ROM, shifter)
   9. 09Secure Element and the I2C network
   10. 10Power/thermal sensors and fans (SMC)
   11. 11Audio: speaker amplifiers and microphone
   12. 12Keyboard and trackpad
   13. 13Input and charging: DC-In, battery, and PBUS
   14. 14CPU power supply: IMVP8 and VR
   15. 15System power (PMIC) and distribution
   16. 16Display: backlight and eDP
   17. 17Storage: NAND and SSD
   18. 18Reference pages and capstone

   Key difference from iPhone/iPad: multi-processor and multi-layer power (discrete VR/FET) instead of a single SoC + single PMU.

4. M5MacBook M-Series18 d▶

   Apple Silicon MacBook board-level delta: reading the M1/M2/M3/M4 architecture where T2 responsibilities move into the SoC, with integrated Secure Enclave, DFU/restore flow, Apple Silicon power tree, and M-series diagnostic differences. Carries the Phase 4 T2/Intel MacBook reflex into M-series MacBooks; T2 is no longer a separate chip.

   1. 01Document structure: table of contents, BOM and mechanicals (M1)
   2. 02The processor (SOC): support, clock/reset and the CIO interface
   3. 03SOC interfaces: display (LPDP/MIPI), PCIe and AOP
   4. 04Processor power rails: CPU, GPU, memory and IO
   5. 05SOC grounding, desense and boot ROM: where does the M1 read its startup code from? (p16-20)
   6. 06Input & charge chain and the Secure Element: how does the board draw energy from outside? (s21-24)
   7. 073.8V always-on power and Iceman VR: how is the first rail born from the main bus? (s25-27)
   8. 08The PMU rail factory: how do the Master and Slave PMUs produce the rail forest from the bus? (s28-35)
   9. 09System power distribution: how do LDOs and load switches deliver the rail to every corner? (s36-40)
   10. 10I2C buses and the SMC: how does the system manage peripherals by 'talking'? (s41-43)
   11. 11Sensors: how does the board 'measure' itself — current, temperature, and motion? (s44-49)
   12. 12USB-C / Thunderbolt: how does one port carry power, data, and display all at once? (s50-59)
   13. 13WiFi/BT and SSD: how do two different peripherals work over the same PCIe path? (s60-65)
   14. 14Display and backlight: why are image and light two separate layers? (s66-70)
   15. 15Audio and trackpad: how do familiar interfaces come together in the last peripherals? (s71-77)
   16. 16Reading the schematic like a reference book: alias, test point, and BOM (s78-90)
   17. 17M1 power-on chain synthesis: end-to-end diagnosis with the '5V to 20V' current signature
   18. 18Capstone: evaluating M1 within its family — the common backbone and M-Series deltas
5. M6Lock & Ethics4 d▶

   1. 01Security architecture: SEP, Secure Element and secure boot
   2. 02Activation / iCloud lock (anti-theft)
   3. 03EFI and firmware locks (device differences)
   4. 04Ethical boundary, data and legitimate process (capstone)

   Device-common lock phase: a capstone unifying the security and lock architecture of all three devices (iPhone/iPad/MacBook).

   Teaches the ARCHITECTURE and the ETHICAL BOUNDARY; contains NO lock-bypass technique (D4).

   Hardware repair is legitimate, crossing an ownership wall without the owner is not; data is not chip-transferable.